Thanks for the information. However, eth1 still doesn’t work correctly. Auto-suggest helps you quickly narrow down your search results by suggesting possible matches as you type. Cadence GEM rev 0x at 0xeb irq It’s almost as if the default config of the PHY is enough to pass data to the eth1 interface even though it hasn’t been configured.
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Hoping to get a pre-release of the Auto-suggest helps you quickly narrow down your search results by suggesting possible matches as you type. I tried it without success. Not sure about the dsa or link.
Add mdio in the top linuc I’ve tried your device tree example as well as different examples found:. We have a custom board with a Zynq using two Marvell 88e PHYs for dual ethernet and have not been able to get eth1 up and running on xilinx-linux eth0 works fine. I assume you use the same interface voltage for both PHY chips. We put our effort to fix this issue marve,l hold, so I don’t have a solution for you. It’s not being released in the petalinux The state machine for this is pretty simple and basically counts the bits as they go out and just inverts the value for one bit period during the desired address bit for example bit 1.
We are not able to run our dual GEM config. Linux Kernel Thanks Panou. Give Kudos to a post which you think is helpful and reply oriented. Verified fix for this problem.
Linux on P + external PHY through RGMII: sl | NXP Community
Cadence GEM rev 0x at 0xeb irq I’ve verified that both PHYs respond when using the u-boot mdio commands, however, when running the Linux kernel code, it appears to ignore or not see the addresses in the device tree, and it also seems to not identify PHY1 correctly, attaching a “Generic PHY” driver to it. I had seen that, but we run both PHYs a 1. When we get back to the issue I will post whatever resolution we marvelk up with. Finally, I saw this thread for Petalinux, which I was not able to locate the patch for, but it seems related.
Did you try running ping with u-boot? Note that it attaches a Generic PHY driver to eth1, and the phy id is: I will dig into the kernel code to see if there is a workaround.
Linux source code: drivers/net/phy/marvell.c (v) – Bootlin
I Have met the same problem, hope could get some ideas from you! Thu Feb 18 According to a Xilinx FAE: However, I don’t see an error in my boot log, and in fact it assigns the PHY id correctly to eth0 and eth1: Could you explain how to implement Xilinx provided patch at each these different steps?
Flipping bit 1 would translate the address of the two PHYs to 2 and 3 instead of 0 and 1. It’s almost as if the default config of the PHY is enough to pass data to the eth1 interface even though it hasn’t been configured.
Linux on P4080 + external PHY through RGMII: slow ping + total freeze without error message
It will doubtless require changes to the linux driver stack to get it working. I will post when I get the new release and test it. I don’t have the Marvell datasheet handy, but recall seeing that when run a 1. I cant try it due to my situation, if you try it can you please give information about Again, this appears to be a jarvell issue.
If 88e1512 both operate at 3.